NuDAQ DAQ-2500/PXI-2500 Series High Performance Analog Output Multi-function Cards User's Guide Recycled Paper
2 • Introduction • D/A FIFO size: 8K samples for DAQ/PXI-2501, and 16K samples for DAQ/PXI-2502 • A/D FIFO size: 2K samples • Versatile trigger so
Introduction • 3 1.3 Specifications Analog Output (AO) • Number of channels: 4-CH for DAQ/PXI-2501, 8-CH for DAQ/PXI-2502 • DA converter: AD7945 •
4 • Introduction Analog Input (AI) • Number of channels: 4 single-ended for DAQ/PXI-2502, 8 single-ended for DAQ/PXI-2501 • AD converter: LTC1416 •
Introduction • 5 General Purpose Timer/ Counter (GPTC) • Number of channel: 2 Up/Down Timer/Counters • Resolution: 16 bits • Compatibility: TTL/CM
6 • Introduction • Power Requirement: +5VDC; 1.6A typical Operating Environment • Ambient temperature: 0 to 55°C • Relative humidity: 10% to 90% n
Introduction • 7 1.4 Software Support ADLINK provides versatile software drivers and packages for users’ dif-ferent approach to building up a system
8 • Introduction 1.4.3 D2K-OCX: ActiveX Controls We suggest customers who are familiar with ActiveX controls and VB/VC++ programming use PCIS-OCX Ac
Installation • 9 2 Installation This chapter describes how to install DAQ/PXI-2500 SERIES cards. The contents of the package and unpacking informatio
10 • Installation 2.2 Unpacking Your DAQ/PXI-2500 SERIES card contains electro-static sensitive com-ponents that can be easily be damaged by static
Installation • 11 2.3 DAQ/PXI-2500 SERIES Layout Figure 2.2 PCB Layout of DAQ-2502/2501 Figure 2.3 PCB Layout of PXI-2502/2501
12 • Installation 2.4 PCI Configuration 1. Plug and Play: As a plug and play component, the board requests an interrupt number via its PCI control
Signal Connections • 13 3 Signal Connections This chapter describes the connectors of DAQ/PXI-2500 SERIES, and the signal connection between DAQ/PXI-
14 • Signal Connections AO_0 1 35 AGND AO_1 2 36 AGND AO_2 3 37 AGND AO_3 4 38 AGND AOEXTREF_A/AI_0 5 39 AGND AI_1 6 40 AGND EXTAT
Signal Connections • 15 Legend : Pin # Signal Name Refer-ence Direction Description 1~4 AO_<0..3> AGND Output Voltage output of DA chan
16 • Operation Theoreym 4 Operation Theorm The operation theories of the DAQ/PXI-2500 series are described in this chapter. The functions include A/
Operation Theorem • 17
18 • Operation Theoreym 4.1 A/D Conversion When using an A/D converter, users should know the properties of the signal to be measured. In addition,
Operation Theorem • 19 4.1.2 Software Polling This is the easiest way to acquire a single A/D data. The A/D converter performs one conversion whenev
20 • Operation Theoreym 4.1.3.1 Scan Timing and Procedure There are 4 counters that need to be specified prior to programmable scans: Counter Name
Operation Theorem • 21 Acquisition_in_progress Scan_start AD_conversion Scan_in_progress 3 Scans, 4 Samples per scan (PSC_Counter=3) Sampling Inter
Copyright 2002~2003 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 1.00: May 16, 2002 Part No : 50-12265-100 The information in this docume
22 • Operation Theoreym Timebase, external input (AFI-1), or General Purpose Timer/Counter Output 0/1. Post-Trigger or Delay-trigger Acquisition wit
Operation Theorem • 23 (NumChan _Counter=4, PSC_Counter=3) Acquisition_in_progress Scan_start AD_conversion Scan_in_progress Acquired & store
24 • Operation Theoreym The hardware temporarily stores the acquired data in the onboard Data FIFO buffer, then transfers the data to the user-define
Operation Theorem • 25 4.2 D/A Conversion DAQ/PXI-2500 series offers flexible and versatile analog output scheme to fit users’ complex field applica
26 • Operation Theoreym Hardware controlled Waveform Generation FIFO is a hardware first-in first-out data queue, which holds temporary digital codes
Operation Theorem • 27 Setting up the DACs Before using the DACs, users should setup the reference source and its polarity. Each DAC has its own ref
28 • Operation Theoreym DAQ/PXI-2500 SERIES can generate standard and arbitrary functions, continuously or piece-wisely. Appendix A demonstrates pos
Operation Theorem • 29 4.2.2.1 Waveform Generation Timing Six counters interact with the waveform to generate different DAWR timing, thus forming d
30 • Operation Theoreym NOTE: The maximum D/A update rate is 1MHz. Therefore the minimum setting of UI_counter is 40. (UC _Counter=4, IC_Counter=3)
Operation Theorem • 31 Delay-Trigger Generation Use delay-trigger when users want to delay the waveform generation after the trigger signal. The del
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32 • Operation Theoreym (UC _Counter=8, IC_Counter=1) 8 update counts, 1 iteration DAWR WFG_in_progress Operation start Trigger Output Wavefor
Operation Theorem • 33 size of a single waveform were larger than that of the FIFO, it needs to be intermittently loaded from the host PC’s memory
34 • Operation Theoreym DLY2_Counter in iterative Waveform Generation To expand the flexibility of Iterative Waveform Generation, DLY2_counter was im
Operation Theorem • 35 (UC _Counter=4, IC_Counter disabled) 4 update counts, infinite iterations DAWR WFG_in_progress Operation start Trigger
36 • Operation Theoreym 4.3 General Purpose Digital I/O DAQ/PXI-2500 SERIES provides 24-line general-purpose digital I/O (GPIO) through a 82C55A ch
Operation Theorem • 37 4.4 General Purpose Timer/Counter Operation Two independent 16-bit up/down timer/counter are embedded in FPGA firmware for us
38 • Operation Theoreym 4.4.2.1 Mode1: Simple Gated-Event Counting In this mode, the counter counts the number of pulses on the GPTC_CLK after the s
Operation Theorem • 39 4.4.2.3 Mode3: Single Pulse-width Measurement In this mode, the counter counts the pulse-width of the signal on GPTC_GATE in
40 • Operation Theoreym 4.4.2.5 Mode5: Single Triggered Pulse Generation This function generates a single pulse with programmable delay and pro-gram
Operation Theorem • 41 4.4.2.7 Mode7: Single Triggered Continuous Pulse Generation This mode is similar to mode 5, except that the counter generates
Table of Contents • i Table of Contents Chapter 1 Introduction ...1 1.1 Features...
42 • Operation Theoreym 4.5 Trigger Sources We provide flexible trigger selections in DAQ/PXI-2500 SERIES. In addi-tion to software trigger, DAQ/PX
Operation Theorem • 43 Trigger Level digital setting Trigger voltage 0xFF 9.92V 0xFE 9.84V --- --- 0x81 0.08V 0x80 0 0x7F -0.08V --- --- 0x0
44 • Operation Theoreym 4.5.2.2 Above-High analog trigger condition Figure 4.5.3 shows the above-high analog trigger condition, the trigger signal
Operation Theorem • 45 4.5.2.4 High-Hysteresis analog trigger condition Figure 4.5.5 shows the high-hysteresis analog trigger condition, the trigger
46 • Operation Theoreym 4.6 Timing Signals In order to meet the requirements for user-specific timing or synchronizing multiple boards, DAQ/PXI-2500
Operation Theorem • 47 4.6.1 System Synchronization Interface SSI uses bi-directional I/O to provide flexible connections between boards. You can c
48 • Calibration 5 Calibration This chapter introduces the calibration process to minimize AD meas-urement errors and DA output errors. DAQ/PXI-2500
Calibration • 49 5.1 Auto-calibration The auto-calibration feature of DAQ/PXI-2500 SERIES facilitates users completing a calibration process, with
50 • Appendix A 6 Appendix A 6.1 Waveform Generation Demonstration Combined with 6 counters, selectable trigger sources, external reference sources,
Appendix A • 51 Standard Function w. Frequency Variant Users can alter the frequency of gener-ated waveforms by driving DAWR from external signal v
ii • Table of Contents 4.1.4.4 Bus-mastering DMA Data Transfer... 23 4.2 D/A Conversion ...
52 • Appendix A By feeding AFI0/AFI1 with PWM source, pulse train from VCO, or any time-varying digital signal, DAQ/PXI-2500 SERIES is capable of ge
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Table of Contents • iii 4.5.2.4 High-Hysteresis analog trigger condition... 45 4.5.2.5 Low-Hysteresis analog trigger cond
iv • How to Use This Guide How to Use This Guide This manual is designed to help you use/understand the DAQ/PXI-2500 SERIES high performance analog o
Introduction • 1 1 Introduction DAQ/PXI-2500 SERIES is an advanced analog output card based on the 32-bit PCI/PXI architecture. High performance des
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