Adlink PXI-2006 User Manual

Advance Technologies; Automate the World.Manual Rev. 2.00Revision Date: April 20, 2006Part No: 50-11020-1030DAQ/PXI-201x/200x4-CH, Simultaneous, Hi

Introduction 11 Introduction The DAQ/PXI-20XX is an advanced data acquisition card basedon the 32-bit PCI architecture. High performance designs and

2Introduction1.1 FeaturesThe DAQ/PXI-20XX Advanced Data Acquisition Card provides thefol-lowing advanced features: X 32-bit PCI-Bus, plug and playX 4-

Introduction 31.2 ApplicationsX Automotive TestingX Cable TestingX Transient signal measurementX ATEX Laboratory AutomationX Biotech measurement

4Introduction1.3 SpecificationsAnalog Input (AI)X Number of channels: 4 differentialX A/D converter: Z 2010: LTC1414 or equivalentZ 2005: A/D7665 or e

Introduction 5X -3dB small signal bandwidth: (Typical, 25°C)X Large signal bandwidth (1% THD): 300 kHzX System Noise: (Typical)Device Input Range Ban

6Introduction2006±10V 1.0 LSBrms 0~10V 1.5 LSBrms±5V 1.0 LSBrms 0~5V 1.6 LSBrms±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms2

Introduction 7X CMRR: (DC to 60Hz, Typical)X Time-base source: Z Internal 40MHz or External clock Input (fmax: 40MHz, fmin: 1MHz, 50% duty cycle) X T

8IntroductionZ Before calibration: ±0.6% of output maxZ After calibration: ±0.1% of output max for DAQ/PXI-2010, ±0.03% of output max for DAQ/PXI-2005

Introduction 9Analog Output (AO)X Number of channels: 2 channel voltage outputX DA converter: LTC7545 or equivalentX Max update rate: 1MS/sX Resoluti

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10 IntroductionZ Before calibration: ±0.8% of output maxZ After calibration: ±0.02% of output maxX General Purpose Digital I/O (G.P. DIO, 82C55A)X Num

Introduction 11Analog Trigger (A.Trig)X Source: Z All analog input channels; external analog trigger (EXTATRIG)X Level: ±Full-scale, internal; ±10V e

12 IntroductionPhysicalX Dimensions: Z 175mm by 107mm for DAQ-20XX Z Standard CompactPCI form factor for PXI-20XXX I/O connector: 68-pin female VHDCI

Introduction 131.4 Software SupportADLINK provides versatile software drivers and packages forusers’ dif-ferent approach to building up a system. ADL

14 Introductionlicense. For detailed information about DAQ-LVIEW PnP, pleaserefer to the user’s guide in the CD.(\\Manual\Software Package\DAQ-LVIEW P

Installation 152 InstallationThis chapter describes how to install the DAQ/PXI-20XX. The con-tents of the package and unpacking information that you

16 InstallationAgain, inspect the module for damages. Press down on all thesocketed IC's to make sure that they are properly seated. Do thisonly

Installation 172.3 DAQ/PXI-20XX LayoutFigure 2-1: PCB Layout of the DAQ-20XXFigure 2-2: PCB Layout of the PXI-20XX

18 Installation2.4 PCI Configuration1. Plug and Play: As a plug and play component, the card requests an interruptnumber via its PCI controller. The s

Signal Connections 193 Signal ConnectionsThis chapter describes the connectors of the DAQ/PXI-20XX, andthe signal connection between the DAQ/PXI-20XX

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20 Signal Connections* SDI for DAQ/PXI-2010 only; NC for DAQ/PXI-2005/2006/2016Legend:PB7 22 56 PB6PB5 23 57 PB4PB3 24 58 PB2PB1 25 59 PB0PC7 26 6

Signal Connections 2117,51 GPTC<0,1>_GATE DGND InputGate of GPTC<0,1>18,52 GPTC<0,1>_OUT DGND InputOutput of GPTC<0,1>19,53 G

22 Signal Connections*PIO means programmable I/OLegend:21 AFI1 DGND InputAuxiliary Func-tion Input 1 (DAWR, DA_START)SSI_TIMEBASE 1 2 DGNDSSI_ADCONV 3

Signal Connections 23SSI_DAWRSSI master: send the DAWR out.SSI slave: accept the SSI_DAWR to replace the internal DAWR signal.SSI_DA_TRIGSSI master:

24 Signal Connections3.2 Analog Input Signal ConnectionThe DAQ/PXI-20XX provides 4 differential analog input channels.The analog signal can be convert

Signal Connections 25Figure 3-1: Single-Ended connectionsIn single-ended configurations, more electrostatic and magneticnoise couples into the single

26 Signal ConnectionsDifferential Connection for Floating Signal SourcesFigure 3-3 shows how to connect a floating signal source toDAQ/PXI-20XX in dif

Operation Theory 274 Operation Theory The operation theory of the functions on the DAQ/PXI-20XX isdescribed in this chapter. The functions include t

28 Operation TheoryDAQ/PXI-2010 AI Data FormatSynchronous Digital Inputs (for DAQ/PXI-2010 only)When each A/D conversion is completed, the 14-bits con

Operation Theory 29due to the variation of the conver-sion time of the A/D con-verters.Table 4-1 and 4-2 illustrate the ideal transfer characteristic

30 Operation TheoryDAQ/PXI-2005/2006/2016 AI Data FormatThe data format of the acquired 16-bit A/D data is Binary coding.Table 7 and 8 illustrate the

Operation Theory 31This method is very suitable for applications that needs to processA/D data in real time. Under this mode, the timing of the A/D c

32 Operation Theorypling A/D card, so the “scan interval” equals to the “samplinginterval”.Example: (Post-trigger acquisition)Set SI_counter = 160PSC_

Operation Theory 33There are 4 trigger modes to start the scan acquisition, pleaserefer to section 4.1for more details. The data transfer mode is dis

34 Operation Theorypost scan count is 0 because there is no sampling after the trig-ger event in pre-trigger acquisition. The total stored amount ofda

Operation Theory 35This situation can be avoided by setting M_enable. If M_enable isset to 1, the trigger signal will be ignored until the first M sc

36 Operation TheoryNote: The PSC_counter is set to 0 in pre-trigger acquisition mode.Middle-Trigger AcquisitionUse middle-trigger acquisition in appli

Operation Theory 37If the trigger event occurs when a scan is in progress, the stored Nscans of data would include this scan, as illustrated in Figur

38 Operation TheoryFigure 4-10: Post triggerDelay Trigger AcquisitionUse delay trigger acquisition in applications where you want todelay the data col

Operation Theory 39data. The total acquired data length = number of enable-chan-nel * PSC_counter.Figure 4-11: Delay triggerNote: When the Delay_coun

Table of Contents iTable of Contents1 Introduction ... 11.1 Features...

40 Operation Theory Figure 4-12: Post trigger with re-triggerBus-mastering DMA Data TransferPCI bus-mastering DMA is necessary for high speed DAQ inor

Operation Theory 41please refer to http://www.plxtech.com for more in-formation onPCI controllers.By using a high-level programming library for high

42 Operation TheoryFigure 4-13: Scatter/gather DMA for data transferIn non-chaining mode, the maximum DMA data transfer size is 2Mdouble words (8M byt

Operation Theory 43put by feeding a sinusoidal signal into the reference input. Therange of the external reference should be within ±10V. Table 4-5an

44 Operation Theorybipolar, and ref-erence source: internal 10V or external AOEX-TREF. Then update the digital values into D/A data registersthrough a

Operation Theory 45Figure 21 shows a typical D/A timing diagram. D/A updates its out-put on each rising edge of DAWR. The meaning of the countersabov

46 Operation Theory Figure 4-15: Post trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)Delay-Tri

Operation Theory 47 Figure 4-16: Delay trigger waveform generation (Assuming the data in the data buffer are 2V, 4V, 6V, 3V, 0V, -4V, -2V, 4V)Post-Tr

48 Operation TheoryIterative Waveform GenerationSet IC_Counter in order to generate iterative waveforms fromthe data of a single waveform. The counter

Operation Theory 49 Figure 4-19: Infinite iterative waveform generation with Post-trigger and DLY2_Counter = 0 (Assuming the data in the data buffer

ii Table of Contents4.5 Trigger Sources ... 57Software-Trigger ...

50 Operation Theoryfor timed waveform gen-eration, which means when it is to stopthe waveform generation. You can apply these 3 modes to stopwaveform

Operation Theory 51 Figure 4-21: Stop mode II Figure 4-22: Stop mode III4.3 Digital I/OThe DAQ/PXI-20XX contains 24-lines of general-purpose digital

52 Operation Theoryinput and is stored with the 14-bit AD data. Please refer to section4.1 for the more details.4.4 General Purpose Timer/Counter Oper

Operation Theory 53GPTC_GATE, and GPTC_OUT are assumed to be active high orrising-edge triggered in the figures. General Purpose Timer/Counter modesE

54 Operation Theory4-24 il-lustrates the operation where initial count = 0, count-upmode.Figure 4-24: Mode 2 OperationMode 3: Single Pulse-width Measu

Operation Theory 55GPTC_GATE is used to enable/disable counting. WhenGPTC_GATE is inactive, the counter halts the current countvalue. Figure 4-26 ill

56 Operation TheoryMode 6: Re-triggered Single Pulse GenerationThis mode is similar to mode5 except that the counter gener-ates a pulse following ever

Operation Theory 57Mode 8: Continuous Gated Pulse GenerationThis mode generates periodic pulses with programmable pulseinterval and pulse-width follo

58 Operation Theorylevel for SRC1 is ±10V and the resolution is 78mV (please refer toTable 4-6), while the trigger range of SRC2 is the full-scale ran

Operation Theory 59Below-Low analog trigger conditionFigure 4-32 shows the below-low analog trigger condition, thetrigger signal is generated when th

List of Tables iiiList of TablesTable 1-1: -3dB small signal bandwidth ... 5Table 1-2: System Noise ...

60 Operation Theoryshould be always higher then the Low_Threshold voltage set-ting.Figure 4-34: Inside-Region analog trigger conditionHigh-Hysteresis

Operation Theory 61High_Threshold voltage determines the hysteresis duration.Note the High_Threshold setting should be always higher thenthe Low_Thre

62 Operation Theory20XX series provides flexible user-controllable timing signals toconnect to external circuitry or additional cards. The whole DAQ t

Operation Theory 63DAQ timing signalsThe user-controllable internal timing-signals contain: (Please referto Section 4.1 for the internal timing signa

64 Operation Theoryshould be TTL-compatible and the minimum pulse widthis 20ns.5. DA_TRIG, the trigger signal for the D/A operation, whichcould be der

Operation Theory 65EXTDTRIG and EXTWFTRIGEXTDTRIG and EXTWFTRIG are dedicated digital trigger inputsignals for A/D and D/A operations respectively. P

66 Operation TheoryEXTTIMEBASEWhen the applications needs specific sampling frequency orupdate rate that the card could not generate from its internal

Operation Theory 67AFI[1]. Note that the AFI[1] is a multi-purpose input, and it canonly be utilized for one function at any one time. AFI[1] cur-re

68 Operation TheoryIn PCI form factor, there is a connector on the top right corner ofthe card for the SSI. Refer to section 2.3 for the connector pos

Operation Theory 69For example: We want to synchronize the A/D operation through the ADCONVsignal for 4 DAQ/PXI-20XX cards. Card 1 is the master, and

iv List of FiguresList of FiguresFigure 2-1: PCB Layout of the DAQ-20XX... 17Figure 2-2: PCB Layout of the PXI-20XX...

70 Operation TheoryVHDCI). Connecting them to any signal source may cause per-manent damage.

Calibration 715 CalibrationThis chapter introduces the calibration process to minimize ADmeas-urement errors and DA output errors.5.1 Loading Calibra

72 Calibrationrecommended for users to adjust the on-board calibration refer-ence except when an ultra-precision cali-brator is available.Note:1. Befo

Warranty Policy 73Warranty PolicyThank you for choosing ADLINK. To understand your rights andenjoy all the after-sales services we offer, please read

74 Warranty Policy3. Our repair service is not covered by ADLINK's guaranteein the following situations:X Damage caused by not following instruct

List of Figures vFigure 4-21: Stop mode II ............... 51Figure 4-22: Stop mode III .....