Adlink PXI-2208 User Manual

Advance Technologies; Automate the World.Manual Rev. 2.01Revision Date: December 04, 2007Part No: 50-11220-2010DAQ-/DAQe-/PXI-2204/2205/2206/220864

iv List of FiguresList of FiguresFigure 2-1: DAQe-2204/2205/2206/2208 Card Layout ... 17Figure 2-2: DAQ-2204/2205/2206/2208 Card Layout ..

88 Warranty Policy3. Our repair service is not covered by ADLINK's guaranteein the following situations:X Damage caused by not following instruct

List of Figures vFigure 4-26: Mode4 Operation... 68Figure 4-27: Mode5 Operation...

vi List of Figures

Introduction 11 Introduction The DAQ-/DAQe-/PXI-2204/2205/2206/2208 card is an advanceddata acquisition card based on the 32-bit PCI or PCI Express®a

2Introduction1.1 FeaturesThe DAQ-/DAQe-/PXI-2204/2205/2206/2208 advanced dataacquisition card has the following features:X 32-bit PCI bus (DAQ/PXI mod

Introduction 31.2 ApplicationsX Automotive TestingX Cable TestingX Transient signal measurementX ATEX Laboratory AutomationX Biotech measurement1.3 S

4IntroductionX Programmable input range:X Operational common mode voltage range: ±11VX Over-voltage protection:Z Power on: Continuous ±30VZ Power off:

Introduction 5X Bandwidth (Typical 25ºC):Device Input rangeSmall signal bandwidth(-3dB)Large signal bandwidth(1% THD)2204/2208±10 V —2000 kHz —±5 V 0

6IntroductionX System Noise (LSBrms, including Quantization, Typical, 25°C)X Input impedance:Z Normal power on: 1 GΩ/100 pFZ Power off: 820 ΩZ Overloa

Introduction 7X Settling time to full-scale step (Typical, 25°C):Device Input Range Condition Settling time2204/2208±10 V • Multiple channels, multip

Copyright 2007 ADLINK TECHNOLOGY INC.All Rights Reserved.The information in this document is subject to change without priornotice in order to improve

8IntroductionX Time-base source:Z Internal 40 MHz or external clock Input (fmax: 40 MHz, fmin: 1 MHz, 50% duty cycle)X Trigger modes: Post-trigger, de

Introduction 9Analog Output (AO)NOTE The DAQ-/DAQe-/PXI-2208 card does not support this function.X Channels: Two-channel analog voltage outputX DA co

10 IntroductionGeneral Purpose Digital I/O (G.P. DIO, 82C55A)X Channels: 24 programmable input/outputX Compatibility: TTLX Input voltage:Z Logic Low:

Introduction 11Analog Trigger (A.Trig)X Source:Z All analog input channelsZ External analog trigger (EXTATRIG)X Level: ±Full-scale, internal; ±10 V e

12 IntroductionPhysicalX Dimensions:Z 175mm by 107mm for DAQ-/DAQe-2204/2205/2206/2208Z Standard CompactPCI form factor for PXI-2204/2205/2206/2208X I

Introduction 131.4 Software SupportADLINK provides versatile software drivers and packages forusers’ different approach to building up a system. ADLI

14 IntroductionDAQ-LVIEW PnP: LabVIEW DriverDAQ-LVIEW PnP contains the VIs, which are used to interfacewith NI’s LabVIEW software package. The DAQ-LVI

Installation 152 InstallationThis chapter describes how to install the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card. The contents of the package and unpac

16 InstallationAgain, inspect the module for damages. Press down on all thesocketed IC's to make sure that they are properly seated. Do thisonly

Installation 172.3 Card LayoutDAQe-2204/2205/2206/2208Figure 2-1: DAQe-2204/2205/2206/2208 Card Layout

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18 InstallationDAQ-2204/2205/2206/2208Figure 2-2: DAQ-2204/2205/2206/2208 Card LayoutPXI-2204/2205/2206/2208Figure 2-3: PXI-2204/2205/2206/2208 Card L

Installation 192.4 PCI ConfigurationPlug and PlayWith support for plug and play, the card requests an interrupt num-ber via its PCI controller. The s

20 Installation

Signal Connections 213 Signal ConnectionsThis chapter describes DAQ-/DAQe-/PXI-2204/2205/2206/2208card connectors and the signal connection between t

22 Signal ConnectionsCN1 Connector* Symbols in “()” are for differential mode connection.AI0 (AIH0) 135 (AIL0) AI32AI1 (AIH1) 236 (AIL1) AI33AI2 (AIH2

Signal Connections 23* Symbols in “()” are for differential mode connection.AI0 (AIH0) 1 35 (AIL0) AI48AI1 (AIH1) 2 36 (AIL1) AI49AI2 (AIH2) 3 37

24 Signal ConnectionsCN2 Connector*Pin 42~45 are SDI<0.3> for DAQ-/DAQe-/PXI-2204; DGND for DAQ-/DAQe-/PXI-2205/2206DA0OUT 1 35 AOGNDDA1OUT 2 3

Signal Connections 25AI32 (AIH32) 1 35 (AIL32) AI80AI33 (AIH33) 2 36 (AIL33) AI81AI34 (AIH34) 3 37 (AIL34) AI82AI35 (AIH35) 4 38 (AIL35) AI83AI36

26 Signal ConnectionsCN1/CN2 Connector Signal DescriptionSignal Name Reference Direction DescriptionAIGND — —Analog ground for AI. All three ground re

Signal Connections 27SDI<0..3>(for 2204 only)DGND InputSynchronous digital inputs. These 4 digital inputs are sampled simultaneously with the a

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28 Signal ConnectionsSSI Connector*Pin 5 and 13 are reserved for DAQ/PXI-2208.SSI Connector Signal Description:SSI_TIMEBASE 1 2 DGNDSSI_ADCONV 3 4 DGN

Signal Connections 293.2 Analog Input Signal ConnectionThe DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides up to64 single-ended or 32 differential a

30 Signal ConnectionsReferenced Single-ended (RSE) ModeIn referenced single-ended mode, all input signals are con-nected to the ground provided by the

Signal Connections 31Differential Input ModeThe differential input mode provides two inputs that respond tosignal voltage difference between them. If

32 Signal Connections

Operation Theory 334 Operation Theory The operation theory of the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card functions are described in this chapter. Th

34 Operation TheoryFigure 4-1: Synchronous Digital Inputs Block DiagramFigure 4-2: Synchronous Digital Inputs TimingNOTE Since the analog signal is sa

Operation Theory 35Table 4-1and Table 4-2 illustrate the ideal transfer characteristicsof various input ranges of the DAQ-/DAQe-/PXI-2204/2205/2206/2

36 Operation TheoryDAQ/DAQe/PXI-2005/2006/2016 AI Data FormatThe data format of the acquired 16-bit A/D data is 2's Comple-ment coding. Table 4-3

Operation Theory 37Software Conversion with Polling Data Transfer Acquisi-tion Mode (Software Polling)This is the easiest way to acquire a single A/D

Using this manual1.1 Audience and scopeThis manual guides you when using ADLINK multi-function DAQ-/DAQe-/PXI-2204/2205/2206/2208 card. The card’s har

38 Operation TheoryProgrammable Scan Acquisition ModeScan Timing and ProcedureIt is recommended that you use this mode if your applicationsneed a fixe

Operation Theory 39Figure 4-3: Scan TimingThere are four trigger modes to start the scan acquisition. Refer tosection 4.1 for details. The data trans

40 Operation TheoryScan with SSHYou can send the SSHOUT signal on CN2 to external S&H cir-cuits to sample and hold all signals if you want to simu

Operation Theory 41ThenX Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2X Sampling interval: 160/40 Ms = 4 µsX Scan interval: 64

42 Operation TheoryTrigger ModesThe DAQ-/DAQe-/PXI-2204/2205/2206/2208 card provides fourtrigger sources (internal software trigger, external analog t

Operation Theory 43Pre-Trigger AcquisitionUse pre-trigger acquisition in applications where you want tocollect data before a trigger event. The A/D s

44 Operation TheoryNote that if a trigger event occurs when a scan is in progress, thedata acquisition won't stop until the scan completes, and t

Operation Theory 45When the trigger signal occurs before the first M scans of data areconverted, the amount of stored data could be fewer than the or

46 Operation TheoryFigure 4-7: Pre-trigger with M_enable=1NOTE The PSC_counter is set to 0 in pre-trigger acquisition mode. Acquisition_in_progress Sc

Operation Theory 47Middle-Trigger AcquisitionUse middle-trigger acquisition in applications where you wantto collect data before and after a trigger

1.3 ConventionsTake note of the following conventions used throughout the man-ual to make sure that you perform certain tasks and instructionsproperly

48 Operation TheoryIf the trigger event occurs when a scan is in progress, the stored Nscans of data would include this scan, as illustrated in Figure

Operation Theory 49Post-Trigger AcquisitionUse post-trigger acquisition in applications where you want tocollect data after a trigger event. The numb

50 Operation TheoryDelay Trigger AcquisitionUse delay trigger acquisition in applications where you want todelay the data collection after the occurre

Operation Theory 51Post-Trigger or Delay-trigger Acquisition with re-triggerUse post-trigger or delay-trigger acquisition with re-triggerfunction in

52 Operation TheoryBus-mastering DMA Data TransferPCI bus-mastering DMA is necessary for high speed DAQ in orderto utilize the maximum PCI bandwidth.

Operation Theory 53Figure 4-13 shows a linked list that is constructed by three DMAdescriptors. Each descriptor contains a PCI address, a localaddres

54 Operation Theory4.2 D/A ConversionNOTE The DAQ-/DAQe-/PXI-2208 card does not support this function.There are two 12-bit D/A output channels availab

Operation Theory 55The D/A conversion is initiated by a trigger source. You mustdecide how to trigger the D/A conversion. The data output will startw

56 Operation TheoryTimed Waveform GenerationThis mode can provide your applications with a precise D/A outputwith a fixed update rate. It can be used

Operation Theory 57Figure 4-14: Typical D/A Timing of Waveform GenerationNOTE The maximum D/A update rate is 1 MHz. Therefore, the minimum setting of

Table of Contents iTable of ContentsTable of Contents... iList of Tables...

58 Operation TheoryTrigger ModesPost-Trigger GenerationUse post-trigger when you want to perform DA waveform rightafter a trigger event occurs. In thi

Operation Theory 59Figure 4-16: Delay Trigger Waveform GenerationPost-Trigger or Delay-Trigger with Re-triggerUse post-trigger or delay-trigger with

60 Operation TheoryIterative Waveform GenerationSet IC_Counter in order to generate iterative waveforms fromthe data of a single waveform. The counter

Operation Theory 61 Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger (DLY2_Counter = 0)Delay2 in Iterative Waveform GenerationTo

62 Operation TheoryStop Modes of Scan UpdateYou can call software stop function to stop waveform genera-tion when it is still in progress. Three stop

Operation Theory 63In stop mode II, after a software stop command is given, thewaveform generation does not stop until a complete singlewaveform is f

64 Operation Theory4.3 Digital I/OThe DAQ-/DAQe-/PXI-2204/2205/2206/2208 card contains 24lines of general-purpose digital I/O (GPIO) which is provided

Operation Theory 65The Basics of Timer/Counter FunctionsEach timer/counter has three inputs that can be controlled viahardware or software. These are

66 Operation TheoryMode1: Simple Gated-Event CountingIn this mode, the counter counts the number of pulses on theGPTC_CLK after the software-start. In

Operation Theory 67Figure 4-24: Mode2 OperationMode3: Single Pulse-width MeasurementIn this mode, the counter counts the pulse-width of the signalon

ii Table of Contents4.1 A/D Conversion... 33DAQ-/DAQe-/PXI-2204/2208 AI Data Format .

68 Operation TheoryMode4: Single Gated Pulse GenerationThis mode generates a single pulse with programmable delayand programmable pulse-width followin

Operation Theory 69Figure 4-27: Mode5 OperationMode6: Re-triggered Single Pulse GenerationThis mode is similar to Mode5 except that the counter gener

70 Operation TheoryMode7: Single Triggered Continuous Pulse GenerationThis mode is similar to Mode5 except that the counter gener-ates continuous peri

Operation Theory 714.5 Trigger SourcesADLINK provides flexible trigger selections in the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card. In addition to the

72 Operation TheoryFigure 4-31: Analog Trigger Block DiagramThe trigger signal is generated when the analog trigger conditionis satisfied. There are f

Operation Theory 73Below-Low Analog Trigger ConditionFigure 4-32 shows the below-low analog trigger condition, thetrigger signal is generated when th

74 Operation TheoryInside-Region Analog Trigger ConditionFigure 4-34 shows the inside-region analog trigger condition,the trigger signal is generated

Operation Theory 75Figure 4-35: High-Hysteresis Analog Trigger ConditionLow-Hysteresis Analog Trigger ConditionFigure 4-36 shows the low-hysteresis a

76 Operation TheoryExternal Digital TriggerAn external digital trigger occurs when a rising edge or a fallingedge is detected on the digital signal co

Operation Theory 774.6 User-controllable Timing SignalsIn order to meet the requirements for user-specific timing andrequirements for synchronizing m

List of Tables iiiList of TablesTable 1-1: Programmabel Input Range ... 4Table 1-2: Bandwidth ...

78 Operation TheoryYou can utilize the flexible timing signals through our softwaredrivers, then simply and correctly connect the signals with theDAQ-

Operation Theory 79width of the TIMEBASE to guarantee correct functional-ities.4. ADCONV, the conversion signal to initiate a single con-version, whi

80 Operation TheoryAuxiliary Function Inputs (AFI)You can use the AFI in applications that take advantage of exter-nal circuitry to directly control t

Operation Theory 81intervals for both A/D and D/A operations. Note that once youchoose the TIMEBASE source, both A/D and D/A operationswill be affect

82 Operation TheorySystem Synchronization InterfaceSSI (System Synchronization Interface) provides the DAQ timingsynchronization between multiple card

Operation Theory 83In PXI form factor, we utilize the PXI trigger bus built on the PXIbackplane to provide the necessary timing signal connections. A

84 Operation TheoryThe SSI/PXI MechanismWe adopt master-slave configuration for SSI/PXI. In a system,for each timing signal, there shall be only one m

Calibration 855 CalibrationThis chapter introduces the calibration process to minimize ADmeasurement errors and DA output errors.5.1 Loading Calibrat

86 Calibration5.2 Auto-calibrationThrough the DAQ-/DAQe-/PXI-2204/2205/2206/2208 card auto-calibration feature, the calibration software measures and

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