Adlink DAQe-2006 User Manual

Advance Technologies; Automate the World.Manual Rev. 2.01Revision Date: March 12, 2007Part No: 50-11219-2000DAQ-/DAQe-/PXI-2016/2010/2006/20054-CH,

iv List of FiguresList of FiguresFigure 2-1: DAQe-2016/2010/2006/2005 Card Layout ... 17Figure 2-2: DAQ-2016/2010/2006/2005 Card Layout ...

List of Figures vFigure 4-31: Analog Trigger Block Diagram... 64Figure 4-32: Below-Low Analog Trigger Condition ...

Introduction 11 Introduction The DAQ-/DAQe-/PXI-2016/2010/2006/2005 card is an advanceddata acquisition card based on the 32-bit PCI or PCI Express®a

2Introduction1.1 FeaturesThe DAQ-/DAQe-/PXI-2016/2010/2006/2005 advanced dataacquisition card has the following features:X 32-bit PCI bus (DAQ/PXI mod

Introduction 31.2 ApplicationsX Automotive TestingX Cable TestingX Transient signal measurementX ATEX Laboratory AutomationX Biotech measurement

4Introduction1.3 SpecificationsAnalog Input (AI)X Number of channels: 4 differentialX A/D converter:Z DAQ-/DAQe-/PXI-2010: LTC1414 or equivalentZ DAQ-

Introduction 5X -3dB small signal bandwidth: (Typical, 25°C)X Large signal bandwidth (1% THD): 300 kHzX System Noise: (Typical)Device Input Range Ban

6Introduction2006±10V 1.0 LSBrms 0~10V 1.5 LSBrms±5V 1.0 LSBrms 0~5V 1.6 LSBrms±2.5V 1.1 LSBrms 0~2.5V 1.7 LSBrms±1.25V 1.1 LSBrms 0~1.25V 1.8 LSBrms2

Introduction 7X CMRR: (DC to 60 Hz, Typical)X Time-base source: Z Internal 40MHz or External clock Input (fmax: 40 MHz, fmin: 1 MHz, 50% duty cycle)

Copyright 2007 ADLINK TECHNOLOGY INC.All Rights Reserved. The information in this document is subject to change without priornotice in order to improv

8IntroductionX Gain error:Z Before calibration: ±0.6% of output maxZ After calibration: ±0.1% of output max for DAQ-/DAQe-/PXI-2010, ±0.03% of output

Introduction 9Analog Output (AO)X Number of channels: Two-channel voltage outputX DA converter: LTC7545 or equivalentX Max update rate: 1 MS/sX Resol

10 IntroductionX Gain error: Z Before calibration: ±0.8% of output maxZ After calibration: ±0.02% of output maxX General Purpose Digital I/O (G.P. DIO

Introduction 11Analog Trigger (A.Trig)X Source:Z All analog input channelsZ External analog trigger (EXTATRIG)X Level: ±Full-scale, internal; ±10 V e

12 IntroductionPhysicalX Dimensions:Z 175mm by 107mm for DAQ-/DAQe-2010/2000Z Standard CompactPCI form factor for PXI-2010/2000X I/O connector: 68-pin

Introduction 131.4 Software SupportADLINK provides versatile software drivers and packages forusers’ different approach to building up a system. ADLI

14 IntroductionDAQ-LVIEW PnP: LabVIEW DriverDAQ-LVIEW PnP contains the VIs, which are used to interfacewith NI’s LabVIEW software package. The DAQ-LVI

Installation 152 InstallationThis chapter describes how to install the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card. The contents of the package and unpac

16 InstallationAgain, inspect the module for damages. Press down on all thesocketed IC's to make sure that they are properly seated. Do thisonly

Installation 172.3 Card LayoutDAQe-2016/2010/2006/2005Figure 2-1: DAQe-2016/2010/2006/2005 Card Layout

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18 InstallationDAQ-2016/2010/2006/2005Figure 2-2: DAQ-2016/2010/2006/2005 Card LayoutPXI-2016/2010/2006/2005Figure 2-3: PXI-2016/2010/2006/2005 Card L

Installation 192.4 PCI ConfigurationPlug and PlayWith support for plug and play, the card requests an interrupt num-ber via its PCI controller. The s

20 Installation

Signal Connections 213 Signal ConnectionsThis chapter describes DAQ-/DAQe-/PXI-2016/2010/2006/2005card connectors and the signal connection between t

22 Signal ConnectionsVHDCI-type (68-pin) Connector*SDI for DAQ/DAQe/PXI-2010 only. NC for DAQ/DAQe/PXI-2005/CH0+ 1 35 CH0-CH1+ 2 36 CH1-CH2+ 3 37 C

Signal Connections 23Legend:Pin # Signal Name Reference Direction Description1~4 CH<0..3>+ CH0<0..3>- InputDifferential positive input fo

24 Signal Connections*PIO means programmable I/O35~38 CH<0..3>- -------- InputDifferential negative input for AI channel <0..3>39 AIGND --

Signal Connections 25SSI Connector (J3)Legend:SSI_TIMEBASE 1 2 DGNDSSI_ADCONV 3 4 DGNDSSI_DAWR 5 6 DGNDSSI_SCAN_START 7 8 DGNDRESERVED 9 10 DGNDSSI

26 Signal Connections3.2 Analog Input Signal ConnectionThe DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides 4 dif-ferential analog input channels. The

Signal Connections 27Figure 3-1: Single-Ended ConnectionsIn single-ended configurations, more electrostatic and magneticnoise couples into the single

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28 Signal ConnectionsDifferential Connection for Floating Signal SourcesFigure 3-3 shows how to connect a floating signal source toDAQ-/DAQe-/PXI-2016

Operation Theory 294 Operation Theory The operation theory of the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card functions are described in this chapter. Th

30 Operation TheoryDAQ-/DAQe-/PXI-2010 AI Data FormatSynchronous Digital Inputs (DAQ-/DAQe-/PXI-2010 only)When each A/D conversion is completed, the 1

Operation Theory 31NOTE Since the analog signal is sampled when an A/D conver-sion starts (falling edge of A/D_conversion signal), while SDI<1..0&

32 Operation TheoryDescription Unipolar Analog Input Range Digital codeFull-scale Range 0V to 10V 0 to +5V 0 to +2.5V 0 to +1.25VLeast significant bit

Operation Theory 33DAQ/DAQe/PXI-2005/2006/2016 AI Data FormatThe data format of the acquired 16-bit A/D data is binary coding.Table 4-3 and Table 4-4

34 Operation TheorySoftware Conversion with Polling Data Transfer Acqui-sition Mode (Software Polling)This is the easiest way to acquire a single A/D

Operation Theory 35Programmable Scan Acquisition ModeScan Timing and ProcedureIt's recommended that this mode be used if your applicationsneed a

36 Operation Theorywhile the minimum should be 1 MHz. Refer to section 4.6 forinformation on user-controllable timing signals.Figure 4-3: Scan TimingT

Operation Theory 37Trigger ModesThe DAQ-/DAQe-/PXI-2016/2010/2006/2005 card provides fourtrigger sources (internal software trigger, external analog

Using this manual1.1 Audience and scopeThis manual guides you when using ADLINK multi-function DAQ-/DAQe-/PXI-2016/2010/2006/2005 card. The card’s har

38 Operation TheoryFigure 4-4: Pre-triggerNote that If the trigger event occurs when a conversion is inprogress, the data acquisition will not stop un

Operation Theory 39When the trigger signal occurs before the first M scans of data areconverted, the amount of stored data could be fewer than the or

40 Operation TheoryFigure 4-7: Pre-trigger with M_enable=1NOTE The PSC_counter is set to 0 in pre-trigger acquisition mode.Middle-Trigger AcquisitionU

Operation Theory 41Figure 4-8: Middle-Trigger with M_enable = 1If the trigger event occurs when a scan is in progress, the stored Nscans of data woul

42 Operation TheoryNOTE The M_counter defined in Middle-Trigger is different from that of the Pre-Trigger. In Middle-Trigger, M_Counter ends counting

Operation Theory 43Delay Trigger AcquisitionUse delay trigger acquisition in applications where you want todelay the data collection after the occurr

44 Operation TheoryPost-Trigger or Delay-trigger Acquisition with re-triggerUse post-trigger or delay-trigger acquisition with re-triggerfunction in a

Operation Theory 45Bus-mastering DMA Data TransferPCI bus-mastering DMA is necessary for high speed DAQ inorder to utilize the maximum PCI bandwidth.

46 Operation Theorylist for the input DMA channel or the output DMA channel.Figure 4-13 shows a linked list that is constructed by threeDMA descriptor

Operation Theory 474.2 D/A ConversionThere are two 12-bit D/A output channels available in the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card. When using D/

1.3 ConventionsTake note of the following conventions used throughout the man-ual to make sure that you perform certain tasks and instructionsproperly

48 Operation TheoryThe D/A conversion is initiated by a trigger source. You mustdecide how to trigger the D/A conversion. The data output will startwh

Operation Theory 49Timed Waveform GenerationThis mode can provide your applications with a precise D/A outputwith a fixed update rate. It can be used

50 Operation TheoryFigure 4-14: Typical D/A Timing of Waveform GenerationNOTE The maximum D/A update rate is 1 MHz. Therefore, the minimum setting of

Operation Theory 51Trigger ModesPost-Trigger GenerationUse post-trigger when you want to perform DA waveform rightafter a trigger event occurs. In th

52 Operation TheoryDLY1_Counter * UI_counter/TIMEBASE), so the delay time canreach a wider range.Figure 4-16: Delay Trigger Waveform GenerationPost-Tr

Operation Theory 53Iterative Waveform GenerationSet IC_Counter in order to generate iterative waveforms fromthe data of a single waveform. The counte

54 Operation Theory Figure 4-19: Infinite Iterative Waveform Generation with Post-trigger and DLY2_Counter = 0NOTES When running infinite iterative wa

Operation Theory 55Stop Modes of Scan UpdateYou can call software stop function to stop waveform genera-tion when it is still in progress. Three stop

56 Operation Theory Figure 4-21: Stop Mode II Figure 4-22: Stop Mode III

Operation Theory 574.3 Digital I/OThe DAQ-/DAQe-/PXI-2016/2010/2006/2005 card contains 24lines of general-purpose digital I/O (GPIO) which is provide

Table of Contents iTable of ContentsTable of Contents... iList of Tables...

58 Operation TheoryGPTC_UPDOWN input controls whether the counter counts up ordown. The GPTC_GATE input is a control signal which acts as acounter ena

Operation Theory 59Mode 2: Single Period MeasurementIn this mode, the counter counts the period of the signal onGPTC_GATE in terms of GPTC_CLK. Initi

60 Operation TheoryFigure 4-25: Mode 3 OperationMode 4: Single Gated Pulse GenerationThis mode generates a single pulse with programmable delayand pro

Operation Theory 61Mode 5: Single Triggered Pulse GenerationThis function generates a single pulse with programmabledelay and pro-grammable pulse-wid

62 Operation TheoryMode 7: Single Triggered Continuous Pulse GenerationThis mode is similar to Mode 5 except that the counter gener-ates continuous pe

Operation Theory 634.5 Trigger SourcesADLINK provides flexible trigger selections in the DAQ-/DAQe-/PXI-2010/2000 Series products. In addition to the

64 Operation TheoryFigure 4-31: Analog Trigger Block DiagramThe trigger signal is generated when the analog trigger conditionis satisfied. There are f

Operation Theory 65Below-Low Analog Trigger ConditionFigure 4-32 shows the below-low analog trigger condition, thetrigger signal is generated when th

66 Operation TheoryNOTE The High_Threshold setting should be always higher than the Low_Threshold voltage setting.Figure 4-34: Inside-Region Analog Tr

Operation Theory 67Low-Hysteresis analog trigger conditionFigure 4-36 shows the low-hysteresis analog trigger condition,the trigger signal is generat

ii Table of Contents4 Operation Theory... 294.1 A/D Conversion...

68 Operation Theory4.6 User-controllable Timing SignalsIn order to meet the requirements for user-specific timing andrequirements for synchronizing mu

Operation Theory 69DAQ timing signalsThe user-controllable internal timing-signals contain (refer to sec-tion 4.1 for the internal timing signal defi

70 Operation Theoryshould be TTL-compatible and the minimum pulse widthis 20 ns.5. DA_TRIG, the trigger signal for the D/A operation, whichcould be de

Operation Theory 71EXTDTRIG and EXTWFTRIGEXTDTRIG and EXTWFTRIG are dedicated digital trigger inputsignals for A/D and D/A operations respectively. R

72 Operation Theoryple the data according to external events. In this mode, theTrigger signal and trigger mode settings are not available.AFI[0] could

Operation Theory 73In PCI form factor, there is a connector on the top right corner ofthe card for the SSI. Refer to section 2.3 for the connector po

74 Operation TheoryThe six internal timing signals could be routed to the SSI or thePXI trigger bus through software drivers. Refer to section 4.6 for

Operation Theory 75Note that when power-up or reset, the DAQ timing signals arereset to use the internal generated timing signals.AI_Trig_Out and AO_

76 Operation Theory

Calibration 775 CalibrationThis chapter introduces the calibration process to minimize ADmeasurement errors and DA output errors.5.1 Loading Calibrat

List of Tables iiiList of TablesTable 1-1: -3dB Small Signal Bandwidth ... 5Table 1-2: System Noise ...

78 Calibration5.2 Auto-calibrationThrough the DAQ-/DAQe-/PXI-2016/2010/2006/2005 card auto-calibration feature, the calibration software measures and

Warranty Policy 79Warranty PolicyThank you for choosing ADLINK. To understand your rights andenjoy all the after-sales services we offer, please read

80 Warranty Policy3. Our repair service is not covered by ADLINK's guaranteein the following situations:X Damage caused by not following instruct